Veriication of Benchmarks 17 and 22 of the Ifip Wg10.5 Benchmark Circuit Suite

This paper reports on the veriication of two of the IFIP WG10.5 benchmarks | the multi-plier and systolic matrix multiplier. The circuit implementations are timed, detailed gate-level descriptions, and the speciication is given using the temporal logic TL n , a quaternary-valued temporal logic. A practical, integrated theorem-proving/model checking system based on the compositional theory for TL n and symbolic trajectory evaluation is used to verify the circuits. A 64-bit version of multiplier circuit (Benchmark 17) containing approximately 28 000 gates takes about 18 minutes of computation time to verify. A 4 4, 32-bit version of the matrix multiplier (Benchmark 22) containing over 110 000 gates take about 170 minutes of computation time to verify. A signiicant timing error was discovered in this benchmark.